The present invention relates generally to semiconductor device manufacturing, and, more particularly, to a structure and method for accurate deep trench resistance measurement.
Dynamic random access memory (DRAM) is a type of semiconductor memory in which the information is stored as data bits in capacitors on a semiconductor integrated circuit. Each bit is typically stored as an amount of electrical charge in a storage cell consisting of a capacitor and a transistor. A practical DRAM circuit generally includes an array of memory cells interconnected by rows and columns, which are referred to as wordlines and bitlines, respectively. Reading data from or writing data to memory cells is achieved by activating selected wordlines and bitlines. More specifically, a trench DRAM memory cell may include a metal-oxide-semiconductor field-effect transistor (MOSFET) connected to a deep trench (DT) capacitor. The transistor includes gate and diffusion regions that are referred to as either drain or source regions, depending on the operation of the transistor.
Typically, the deep trench capacitor is formed in a silicon substrate using one or more conventional techniques, such as reactive ion etching (RIE), with photoresist or other materials as a mask to cover the areas where trench formation is not desired. The trench is typically filled with a conductor material (most commonly n-type doped polysilicon), which serves as one plate of the capacitor, usually referred to as the “storage node.” The second plate of the capacitor is typically formed by outdiffusion of an n-type doped region surrounding the lower portion of the trench, usually referred to as the “buried plate.” A node dielectric layer, which may include, for example, silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), tantalum oxide (Ta2O5), aluminum oxide (Al2O3), or any other dielectric material, is provided to separate the storage node and buried plate, thereby forming the capacitor.
One significant parameter of interest in the manufacture of DRAM deep trench capacitors is the distributed resistance of the polysilicon fill material (i.e., the storage node material), since the time constant (and thus operating speed of a semiconductor device) is limited by the resistance. The traditional practice has been to estimate this polysilicon resistance value, using the known resistivity of blanket-deposited polysilicon in combination with the DT geometry. However, the accuracy of such an estimation-based approach is less than could otherwise be obtained by means of some type of direct measurement.
U.S. Pat. No. 6,627,513 to Wu, et al. describes one possible method for measuring trench resistance. However, there are at least two potential drawbacks associated with the approach described therein. First, the structure actually used for the resistance measurement is quite different from the actual functional deep trenches that would be formed in a DRAM array environment, in that the test structure calls for the formation of a collar along the entire length of the trench, followed by the removal of the collar in trench bottom. Moreover, based upon the described ion implantation energy used to dope the substrate and n-well in the Wu patent, it becomes readily apparent to one skilled in the art that the approach therein results in a much shorter version of a deep trench with respect to a functional deep trench. Thus, a direct measurement of such a test trench structure would not accurately reflect the resistance of fully defined deep trench.
Furthermore, the applicability of the Wu approach to a fully defined deep trench (by simply increasing the implant energy) is not practical, since standard implantation equipment is not capable of implanting an n-type dopant to a depth of about 7-8 microns. Accordingly, it would be desirable to be able to implement a structure and method for accurately measuring deep trench resistance, for a full-depth trench, in either an integrated or a short-loop process so as to result in minimal disruption of an existing process of record.